1. Field of the Invention
The present invention relates to BIST architectures and more particularly, to an architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions.
2. Description of the Related Art
As embedded memory sizes continue to increase, overall BIST testing time will also increase; hence, novel schemes that reduce testing time while maintaining test integrity and diagnostic resolution are of great value.
In current and future designs, there is a need to separate and distribute memory arrays across a die, placing them near the functional units that they are associated with. To associate a BIST with each memory array would consume a considerable amount of chip real estate. An architecture that provides for a single BIST that could test all the memories without significant extra time for testing would be advantageous given the above stated trend.
As embedded memory performance and complexity continues to increase, BIST testing at application speeds also becomes more important; hence, novel schemes that support increased BIST performance, while still maintaining BIST flexibility and minimizing design schedule and chip real estate impact are of great value. An architecture that allows for a single BIST that can test a diverse range of memory types and sizes at a number of different performance points would be advantageous.